Pattern recognition in multi-synaptic photonic spiking neural networks based on a DFB-SA chip
基于DFB-SA芯片的多突触光子尖峰神经网络模式识别
DFB−SAチップに基づくマルチシナプス光子スパイクニューラルネットワークパターン認識
DFB-SA 칩 기반 다중 시냅스 광자 스파이크 신경망 모드 인식
Reconocimiento de patrones de red neuronal de pico fotónico multisináptico basado en chips dfb - SA
Reconnaissance de modèle de réseau de neurones à pointes photoniques multisynaptiques basée sur la puce DFB - sa
Многосинаптическое распознавание пиковых нейронных сетей на основе чипов DFB - SA
¹ State Key Laboratory of Integrated Service Networks, State Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, Xidian University, Xi'an 710071, China
中国 西安 西安电子科技大学 综合业务网国家重点实验室 宽带隙半导体技术国家重点学科实验室
² Yongjiang Laboratory, Ningbo 315202, China
中国 宁波 甬江实验室
³ Key Laboratory of Intelligent Optical Sensing and Manipulation, Ministry of Education, the National Laboratory of Solid State Microstructures, the College of Engineering and Applied Sciences, Institute of Optical Communication Engineering, Nanjing University, Nanjing 210023, China
中国 南京 南京大学光通信工程研究中心 智能光传感与调控技术教育部重点实验室 固体微结构物理国家重点实验室
Spiking neural networks (SNNs) utilize brain-like spatiotemporal spike encoding for simulating brain functions. Photonic SNN offers an ultrahigh speed and power efficiency platform for implementing high-performance neuromorphic computing. Here, we proposed a multi-synaptic photonic SNN, combining the modified remote supervised learning with delay-weight co-training to achieve pattern classification. The impact of multi-synaptic connections and the robustness of the network were investigated through numerical simulations.
In addition, the collaborative computing of algorithm and hardware was demonstrated based on a fabricated integrated distributed feedback laser with a saturable absorber (DFB-SA), where 10 different noisy digital patterns were successfully classified. A functional photonic SNN that far exceeds the scale limit of hardware integration was achieved based on time-division multiplexing, demonstrating the capability of hardware-algorithm co-computation.
